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ST
Sitronix
FEATURES
CGROM :10240 bits(256chars 5 x 8 dots) CGRAM :320 bits(8 chars 5 x 8 dots) DDRAM :64 bytes(16 x 4 ) ICONRAM :80 bits Low power operation support: -- 2.4 to 3.6V Wide range of LCD driver power -- 3.0 to 7.0V 4-bit or 8-bit MPU interface for both 68 and 80 series 4 pin clock synchronized serial interface COM/SEG bi-directional setting Voltage converter/regulator/follower/bias circuit built in 26 common x 80 segment liquid crystal display driver 32 steps electronic volume control Wide range of instruction functions: return home, display on/off, cursor on/off, display character blink, double height, line shift, function set, power and bias control Hardware reset pin available Internal oscillator or external clock Power save mode for low power consumption Bare Chip available
ST7093
26 COM / 80 SEG LCD CONTROLLER/DRIVER
GENERAL DESCRIPTION
The ST7093 dot-matrix liquid crystal display controller can drive LSI displays alphanumeric, Japanese kana characters, and symbols. It can be configured to drive a dot-matrix liquid crystal display under the control of a 4bit, 8 bit or 4 pin clock synchronized serial bus interface. For 4 bit and 8 bit bus interface both 68 series and 80 series type are available. Since all the functions such as display RAM, character generator, liquid crystal driver, oscillator and voltage control functions required for driving a dot-matrix liquid crystal display are internally provided on one chip, a minimal system can be interfaced with this controller/driver. The ST7093 character generator ROM is extended to generate 256 5 x 8 dot character fonts. The low power supply (2.4V to 3.6V) of the ST7093 is suitable for any portable battery-driven product requiring low power dissipation. The ST7093 LCD driver consists of 26 common signal drivers and 80 segment signal drivers with COG gold bump available.
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BLOCK DIAGRAM
RESETB Reset Circuit
CK CPG Timing Generator DIRS
PS IF MI CSB RS RW_WR E_RD MPU interface Instruction Register (IR) 25-bit shift registe Display data RAM (DDRAM) 64X8bits Common Signal Driver
COM1 to COM24
COMI1 COMI2
Instruction Decoder DB4 to DB7 Input/ Output Buffer DB0 to DB3 Data Register (DR) Address Counter
80-bit shift register
80-bit latch circuit
Segment Signal Driver
SEG1 to SEG80
LCD Drive Voltage Selector ICON RAM 80 bits Character generator RAM 320 bits (CGRAM) Character generator ROM 10,240 bits (CGROM) Cursor blink control
Parallel/Serial Converter VDD GND Voltage booster
LCD Power Circuit
Voltage regulator Bias Circuit
CAP1+ CAP1- CAP2+ CAP2-
Vout Vext
REF
V0 V1 V2
V3
V4 VR
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PAD DIMENSIONS (COB)
166 167
........................
(0,0)
87 86
..
179
..
74 73
81.0m x 64.8m 64.8m x 81.0m 63.0m x 84.6m 64.8m x 81.0m 3/43 2003/09/23
................................
1
Chip Size Min Pitch Pad Size : 6775 X 1872 m : 72 m (Seg.) : PAD No. 1~73 : PAD No. 74~86 : PAD No. 87~166 : PAD No. 167~179
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PAD DIMENSIONS (COG)
166 167
........................
(0,0)
87 86
..
..
74 73
68.4m x 52.2m 52.2m x 68.4m 50.4m x 72m 52.2m x 68.4m
50um 10um 10um 50um
179
................................
1
Chip Size Min Pitch Bump Size : 6775 X 1872 m : 72 m (Seg.) : PAD No. 1~73 : PAD No. 74~86 : PAD No. 87~166 : PAD No. 167~179 Bump Height : 18 m (Typ.) COG Align Key Coordinate
10um
50um
50um
10um
(-3270.5,819.3)
(3270.5,819.3)
30um
30um
30um
30um
30um
30um
30um 60um 30um 30um 30um
(-2917,-731.5)
(2672,-547)
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PAD LOCATION
Table 2. PAD Center Coordinates
NO. PAD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 PAD NAME DUMMY DUMMY DUMMY DUMMY DUMMY RS VSS RW VDD E CSB D7 D6 D5 D4 D3 D2 D1 D0 VDD VDD VDD VSS VSS VSS V4 V4 V3 V3 V2 V2 V1 V1 V0 V0 V0 V0 VR VR VOUT VOUT CAP2N CAP2N CAP2P CAP2P CAP1N CAP1N CAP1P CAP1P VEXT VSS VSS VSS VR DUMMY REF DIRS VDD VDD VDD NO. PAD 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 PAD NAME CK VSS PSB VDD IF VSS MI VDD RESETB TEST3 TEST2 TEST1 TEST0 COMI1 COM[1] COM[2] COM[3] COM[4] COM[5] COM[6] COM[7] COM[8] COM[17] COM[18] COM[19] COM[20] SEG[1] SEG[2] SEG[3] SEG[4] SEG[5] SEG[6] SEG[7] SEG[8] SEG[9] SEG[10] SEG[11] SEG[12] SEG[13] SEG[14] SEG[15] SEG[16] SEG[17] SEG[18] SEG[19] SEG[20] SEG[21] SEG[22] SEG[23] SEG[24] SEG[25] SEG[26] SEG[27] SEG[28] SEG[29] SEG[30] SEG[31] SEG[32] SEG[33] SEG[34] NO. PAD 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 PAD NAME SEG[35] SEG[36] SEG[37] SEG[38] SEG[39] SEG[40] SEG[41] SEG[42] SEG[43] SEG[44] SEG[45] SEG[46] SEG[47] SEG[48] SEG[49] SEG[50] SEG[51] SEG[52] SEG[53] SEG[54] SEG[55] SEG[56] SEG[57] SEG[58] SEG[59] SEG[60] SEG[61] SEG[62] SEG[63] SEG[64] SEG[65] SEG[66] SEG[67] SEG[68] SEG[69] SEG[70] SEG[71] SEG[72] SEG[73] SEG[74] SEG[75] SEG[76] SEG[77] SEG[78] SEG[79] SEG[80] COMI2 COM[24] COM[23] COM[22] COM[21] COM[16] COM[15] COM[14] COM[13] COM[12] COM[11] COM[10] COM[9]
X
-3249 -3159 -3069 -2979 -2889 -2799 -2709 -2619 -2529 -2439 -2349 -2259 -2169 -2079 -1989 -1899 -1809 -1719 -1629 -1539 -1449 -1359 -1269 -1179 -1089 -999 -909 -819 -729 -639 -549 -459 -369 -279 -189 -99 -9 81 171 261 351 441 531 621 711 801 891 981 1071 1161 1251 1341 1431 1521 1611 1701 1791 1881 1971 2061
Y
-821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821
X 2151 2241 2331 2421 2511 2601 2691 2781 2871 2961 3051 3141 3231 3272 3272 3272 3272 3272 3272 3272 3272 3272 3272 3272 3272 3272 2868 2796 2724 2652 2580 2508 2436 2364 2292 2220 2148 2076 2004 1932 1860 1788 1716 1644 1572 1500 1428 1356 1284 1212 1140 1068 996 924 852 780 708 636 564 492
Y -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -821 -454 -364 -274 -184 -94 -4 86 176 266 356 446 536 626 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811
X 420 348 276 204 132 60 -12 -84 -156 -228 -300 -372 -444 -516 -588 -660 -732 -804 -876 -948 -1020 -1092 -1164 -1236 -1308 -1380 -1452 -1524 -1596 -1668 -1740 -1812 -1884 -1956 -2028 -2100 -2172 -2244 -2316 -2388 -2460 -2532 -2604 -2676 -2748 -2820 -3272 -3272 -3272 -3272 -3272 -3272 -3272 -3272 -3272 -3272 -3272 -3272 -3272
Y 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 811 626 536 446 356 266 176 86 -4 -94 -184 -274 -364 -454
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PIN DESCRIPTION NAME
RS
I/O Interfaced
I MPU
FUNCTION
Select registers. 0: Instruction register (for write) address counter (for read) 1: Data register (for write and read) Select read or write. In 68 mode In 80 mode 0: Write 0: Write 1: Read 1: Not active Starts data read/write. In 68 mode In 80 mode 0: Not active 0: Read 1: Enable 1: Not active Four high order bi-directional tristate data bus pins. Used for data transfer and receive between the MPU and the ST7093. In serial interface mode DB7 is SI (input data), DB6 is SCL (serial clock). Four low order bi-directional tristate data bus pins. Used for data transfer and receive between the MPU and the ST7093. These pins are not used during 4-bit operation. (Fixed high) Chip select signal. Active low. Reset signal. Active low. External clock input pin. it must be fixed to "Vss" , when the internal oscillator circuit is used. In case of the external clock mode, CK is used as the clock and OS bit should be turn off. Interface selection 0: 80 mode interface 1: 68 mode interface SEG direction selection 0: SEG1 SEG80 1: SEG80 SEG1 Interface selection valid when PS=1 0: 4 bit bus mode 1: 8 bit bus mode Interface selection 0: serial mode 1: 4bit/ 8bit bus mode Common signals. COMI1 and COMI2 are the same signal Segment signals Capacitor connection pins for voltage booster
RW_WR
I
MPU
E_RD
I
MPU
DB4 to DB7
I/O
MPU
DB0 to DB3 CSB RESETB CK MI DIRS IF PS COM1 to COM24 COMI1,COMI2 SEG1 to SEG80 CAP1+, CAP1CAP2+, CAP2Vout VR
I/O I I I I I I I O O O I/O I
MPU MPU MPU MPU MPU MPU MPU MPU LCD LCD
Voltage booster output pin Voltage adjust pin between V0 and VSS Reference voltage selection pin REF I MPU 0: internal regulator is selected 1: external reference voltage input to Vext Vext I/O External reference voltage input Power supply for LCD drive V0 to V4 Power supply V0 - Vss = 7 V (Max) VDD , GND Power supply VDD : 2.4V to 3.6V, GND: 0V Test 0 to Test3 I Test pin. open Note: 1. V0>=V1>=V2>=V3>=V4>=VSS must be maintained
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FUNCTION DESCRIPTION System Interface
This chip has all two kinds of parallel interface type with MPU : 4-bit bus and 8-bit bus. 4-bit bus or 8-bit bus is selected by IF pin. During read or write operation, two 8-bit registers are used. One is data register (DR), the other is instruction register(IR). The data register(DR) is used as temporary data storage place for being written into or read from DDRAM/CGRAM, target RAM is selected by RAM address setting instruction. Each internal operation, reading from or writing into RAM, is done automatically. So to speak, after MPU reads DR data, the data in the next DDRAM/CGRAM address is transferred into DR automatically. Also after MPU writes data to DR, the data in DR is transferred into DDRAM/CGRAM automatically. The Instruction register(IR) is used only to store instruction code transferred from MPU. MPU cannot use it to read instruction data. To select register, use RS input pin in 4-bit/8-bit bus mode and serial mode. Table 1. Various kinds of operations according to RS and R/W bits for 68 interface. RS RW_WR Operation L L Instruction Write operation (MPU writes Instruction code into IR) L H Read address counter (DB0 ~ DB6) H L Data Write operation (MPU writes data into DR) H H Data Read operation (MPU reads data from DR) Table 1.1. Various kinds of operations according to RS and R/W bits for 80 interface. RS RW_WR E_RD Operation L L H Instruction Write operation (MPU writes Instruction code into IR) L H L Read address counter (DB0 ~ DB6) H L H Data Write operation (MPU writes data into DR) H H L Data Read operation (MPU reads data from DR) Address Counter (AC) Address Counter(AC) stores DDRAM/CGRAM address, transferred from IR. After writing into (reading from) DDRAM/CGRAM, AC is automatically increased (decreased) by 1. When RS = "Low" and R/W = "High", AC can be read through DB0 ~ DB6 ports. RS RW_WR E_RD DB0-DB7
Instr Dummy read
Circuit
ite
RAM read
Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (68 Series MPU Mode)
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RS RW_WR E_RD DB0-DB7
Instruction write Dummy read
RAM read
Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (80 Series MPU Mode)
RS RW_WR E_RD
Upper lower Upper lower
4-bit 4-bit
Upper lower
4-bit 4-bit
DB4-DB7
4-bit
4-bit
Instruction write
Dummy read
RAM read
Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (68 Series MPU Mode)
RS RW_WR E_RD
Upper lower Upper lower
4-bit 4-bit
Upper lower
4-bit 4-bit
DB0-DB7
4-bit
4-bit
Instruction write
Dummy read
RAM read
Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (80 Series MPU Mode)
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Display Data RAM (DDRAM)
Display data RAM (DDRAM) stores display data represented in 8-bit character codes. Its extended capacity is 64 x 8 bits, or 64 characters. The area in display data RAM (DDRAM) that is not used for display can be used as general data RAM. See Figure 1 for the relationships between DDRAM addresses and positions on the liquid crystal display. The DDRAM address (ADD ) is set in the address counter (AC) as hexadecimal. DDRAM address and corresponding display position There is 4 line display data stored in DDRAM but only 2 lines are shown at a time. (2 line mode) Hidden lines can be displayed by issuing line shift instruction.
Figure 1 DDRAM Address
High Low Order Order bits bits AC AC AC AC AC AC AC AC
Example: DDRAM Address 37H 0 1 1 0 1 1 1
Display Position 00 COM1~8 COM9~16 10
1 2 3 4 5 6 7 8 9 10 11 12
13 14 15 16
0C 0D 1C 1D 0E 1E 0F 1F
01 11
02 12
03 13
04 14
05 15
06 16
07 17
08 18
09 19
0A 1A
0B 1B
Hidden Hidden
20 30
21 31
22 32
23 33
24 34
25 35
26 36
27 37
28 38
29 39
2A 3A
2B
2C 2D
2E
2F 3F
3B 3C 3D 3E
Figure 2 2-Line Mode by 16-Character Display Example
Display Position 00 COM1~8 COM9~16 10
1 2 3 4 5 6 7 8 9 10 11 12
13 14 15 16
0C 0D 1C 1D 0E 1E 0F 1F
01 11
02 12
03 13
04 14
05 15
06 16
07 17
08 18
09 19
0A 1A
0B 1B
COM17~24 20 Hidden 30
21 31
22 32
23 33
24 34
25 35
26 36
27 37
28 38
29 39
2A 3A
2B
2C 2D
2E
2F 3F
3B 3C 3D 3E
Figure 3 3-Line Mode by 16-Character Display Example
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Character Generator ROM (CGROM) The character generator ROM generates 5 x 8 dot character patterns from 8-bit character codes. It can generate 256 5 x 8 dot character patterns. User-defined character patterns are also available by mask-programmed ROM. Character Generator RAM (CGRAM) In the character generator RAM, the user can rewrite character patterns by program. For 5 x 8 dots, eight character patterns can be written. Write into DDRAM the character codes at the addresses shown as the left column of Table 4 to show the character patterns stored in CGRAM. See Table 5 for the relationship between CGRAM addresses and data and display patterns. Areas that are not used for display can be used as general data RAM. Timing Generation Circuit The timing generation circuit generates timing signals for the operation of internal circuits such as
DDRAM, CGROM and CGRAM. RAM read timing for display and internal operation timing by MPU access are generated separately to avoid interfering with each other. Therefore, when writing data to DDRAM, for example, there will be no undesirable interference, such as flickering, in areas other than the display area.
LCD Driver Circuit LCD Driver circuit has 26 common and 80 segment signals for LCD driving. Data from CGRAM/CGROM is transferred to 80 bit segment latch serially, and then it is stored to 80 bit shift latch. When each common is selected by 26 bit common register, segment data also output through segment driver from 80 bit segment latch. Cursor/Blink Control Circuit It can generate the cursor or blink in the cursor/blink control circuit. The cursor or the blink appears in the digit at the display data RAM address set in the address counter.
Applicable Panel Size Font 5X8 Display 2 Line X 16 Char 3 Line x 16 Char Duty 1/17 1/25 Contents of outputs 2x16 characters + 80icons 3x16 characters + 80icons
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Correspondence between Character Codes and Character Patterns
Table 4-1
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Table 4-2
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NO.7093-0C
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Character Code CGRAM Character Patterns (DDRAM Data) Address (CGRAM Data) b7 b6 b5 b4 b3 b2 b1 b0 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
Table 5 Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character patterns (CGRAM Data) Notes:
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 -
1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0
1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0
1 1 1 1 1 1 1 0 1 0 0 1 1 0 0 0
1 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0
1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0
1. Character code bits 0 to 2 correspond to CGRAM address bits 3 to 5 (3 bits: 8 types). 2. CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line CGRAM address (b2,b1,b0) = (1,1,1) is the cursor line. Should the cursor position is displayed with CGRAM character the 8th line output data will become (1,1,1,1,1). 3. Character pattern row positions correspond to CGRAM data bits 0 to 4 (bit 4 being at the left). 4. 1 for CGRAM data corresponds to display selection and 0 to non-selection. "-": Indicates no effect.
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Relationship between ICONRAM address and display pattern
When ICONRAM data is filled the corresponding position displayed is described as the following table. ICONRAM bits D7 D6 D5 D4 D3 D2 00H S1 S2 S3 01H S6 S7 S8 02H S11 S12 S13 : : : : : : : 0DH S66 S67 S68 0EH S71 S72 S73 0FH S76 S77 S78 Notes : S1~S80 corresponds to display position of SEG1 ~ SEG80. ICONRAM address D1 S4 S9 S14 : S69 S74 S79 D0 S5 S10 S15 : S70 S75 S80
Segment data shift direction corresponding to DIRS pin setting
Segment data shift direction can be altered by setting values to the DIRS pin described as the following table. DIRS Low High S1 S80 Segment data shift direction S2 S3 S4 S5 ............... S78 S79 S80 S79 S78 S77 S76 ............... S3 S2 S1
Common data shift direction corresponding to S
Common data shift direction can be altered by setting the S value through function set instruction. The directions corresponding to S value is described as the following table.
S Low High
COM1 COM2 COMI1(COMI2)
Common data shift direction COM3 ........... COM15 COM24 COMI1(COMI2) COM24 COM15 .......... COM3 COM2 COM1
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Instructions
There are four categories of instructions that: Designate ST7093 functions, such as display format, data length, etc. Set internal RAM addresses Perform data transfer with internal RAM Others
Instruction Table:
Instruction Code Instruction RS RW DB DB DB DB DB DB DB DB 7 0 6 0 5 0 4 0 3 0 2 0 1 1 0 Set DDRAM address to "00H" from AC and return cursor to its 0 0 x original position if shifted. The contents of DDRAM are not changed. Set double height mode (DH2, DH1) = (0,0) : normal (default) (0,1) :1)2-line mode COM1..COM16 is a double height COM17..COM24 is no use Double height Mode Set 0 0 0 0 0 0 1 0
DH2 DH1
Description
Execution Time
Return Home
80us
2) 3-line mode COM1..COM16 is a double height COM17..COM24 is normal (1,0) : 1) 2-line mode normal display 2) 3-line mode COM1..COM8 is normal COM9..COM24 is a double height l (1,1) : normal C=0 : cursor off(default) C=1: cursor on 0 0 0 0 1 0 1 C B D B=0 : blink off (default) B=1: blink on D=0 : display off(default) D=1: display on 0 0 0 0 0 0 1 1 OS PS OS=0 : OSC off(default) OS=1 : OSC on PS=0 : save off(default) PS=1 : save on (Display line mode) N=0 : 2 line display(default) N=1 : 3 line display (Shifting direction of COM) 80us 80us 80us
Display control Power save control
Function Set
0
0
0
0
0
1
0
N
S
CG
S=0 : 1) 2-line mode COM1 COM16(default) 2) 3-line mode COM1 COM24(default) S=1 : 1) 2-line mode COM16 2) 3-line mode COM24 (Select CGRAM or CGROM) CG=0 : CGROM(default) CG=1 : CGRAM COM1 COM1
80us
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Instruction Code Instruction RS RW DB DB DB DB DB DB DB DB 7 6 5 4 3 2 1 0 (LS2,LS1) = (0,0) : DDRAM line 1 on top Line shift mode 0 0 0 0 0 1 1 0 LS2 LS1 (0,1) : DDRAM line 2 on top (1,0) : DDRAM line 3 on top (1,1) : DDRAM line 4 on top 80us Description Execution Time
Bias control
0
0
0
0
0
1
1
1
x
BS BS=0 : 1/5 bias(default) BS=1 : 1/4 bias
80us
VC=0 : voltage booster off(default) =1 : voltage booster on Power control 0 0 0 0 1 0 0 VC VR VF VR=0 : voltage regulator off(default) =1 : voltage regulator on VF =0 : voltage follower off(default) =1 : voltage follower on 80us
ICONRAM address
0
0
0
1
0
AC AC AC AC AC Set ICONRAM address in address counter 4 3 2 1 0 EV addr : 10H
80us
CGRAM/ DDRAM address 0 0 1
AC AC AC AC AC AC AC 6 5 4 3 2 1 0
Set CGRAM/DDRAM address DDRAM : 00H ~ 3FH CGRAM : 40H ~ 7FH 80us
Write data to RAM
1
0
D7 D6 D5 D4 D3 D2 D1 D0
Write data into internal RAM (DDRAM/CGRAM)
80us
Read data from RAM
1
1
D7 D6 D5 D4 D3 D2 D1 D0
Read data from internal RAM (DDRAM/CGRAM)
80us
Note: 1. "x" Don't care 2. Make sure to use enough delay time(100us) between instruction
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INSTRUCTION DESCRIPTION
Return Home
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
0
0
0
0
0
0
0
0
1
x
Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. Return cursor to the left edge on first line of display. Double height mode
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
0
0
0
0
0
0
1
0
DH2 DH1
Set double height mode DH2 Low DH1 Low Action Normal display (default) 1) 2-line mode COM1..COM16 is a double height Low High COM17..COM24 is no use 2) 3-line mode COM1..COM16 is a double height COM17..COM24 is normal 1) 2-line mode normal display High Low 2) 3-line mode COM1..COM8 is normal COM9..COM24 is a double height High High Normal display
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3 Line mode normal display (DH2,DH1=0,0)
3 Line mode COM1 ..16 is a double height line, COM17 .. 24 is normal (DH2,DH1=0,1)
COM1 ..8 is normal , COM9 .. 24 is a double height line (DH2.DH1 = 1,0)
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2 line mode normal display (DH2,DH1=0,0)
2 line mode COM1 ..16 is a double height line (DH2,DH1=0,1)
Bias Control
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
0
0
0
0
0
1
1
1
*
BS
Bias control instruction will set the internal bias level generator BS = "Low" (default) : 1/5 bias = "High" : 1/4 bias Display control
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
0
0
0
0
1
0
1
C
B
D
Control display/cursor/blink ON/OFF 1 bit register. C : Cursor ON/OFF control bit When C = "High", cursor is turned on. When C = "Low", cursor is disappeared in current display. The cursor data performs exclusive OR with any display data on the cursor line. B : Cursor Blink ON/OFF control bit Ver 2.1 20/43 2003/09/23
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When B = "High", C="High" then performs alternate between reverse display character and display character at the cursor position. If C="Low" then display is normal regardless of B. When B = "Low", blink is off. D : Display ON/OFF control bit When D = "High", entire display is turned on. When D = "Low", display is turned off, but display data is remained in DDRAM. Function set
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
0
0
0
0
0
1
0
N
S
CG
(Display line mode) N : Number of display lines ="Low" (default) : 2 lines COM1~COM16 are displayed ="High" : 3 lines COM1~COM24 are displayed (Shifting direction of COM) S : Common data shift direction ="Low" (default) : 1) 2-line mode COM1 COM16(default) 2) 3-line mode COM1 COM24(default) ="High" : 1) 2-line mode COM16 2) 3-line mode COM24 COM1 COM1
(Select CGRAM or CGROM) CG: CGRAM enable bit ="Low" (default) : CGRAM is disabled, CGROM data pattern will appear on the display instead. ="High" : CGRAM enabled. Power save set
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
0
0
0
0
0
0
1
1
OS PS
OS : Oscillator on/off bit When OS = "High", internal oscillator is enabled. When OS = "Low" (default), internal oscillator is disabled PS : Power save mode When PS = "Low" (default) Power save mode is disabled. When PS = "High" , Power save mode is enabled.
Ver 2.1
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2003/09/23
ST7093
Set ICONRAM Address
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
0
0
0
1
0
AC AC AC AC AC
Set ICONRAM address to AC. Before writing or reading data, set ICONRAM address should be performed. After each write or read the address counter will increase 1 automatically. 5 bit ICON is stored in each data byte. If (C,B) = (1,1) then ICON display will blink. ICONRAM address is from 00H to 0FH. Address 10H is reserved for electronic volume level setting.
Set CGRAM/DDRAM Address
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
0
0
1
AC AC AC AC AC AC AC
Set CGRAM /DDRAM address to AC. CGRAM and DDRAM share the same address space. Before accessing CGRAM/DDRAM, set CGRAM/DDRAM address should be performed. Address counter will automatically increase by 1 after each write or read operation. After accessing 7FH the address will reset to 00H. Addr 00H 10H 20H 30H 40H 50H 60H 70H 0 1 2 3 4 5 6 7 8 9 A B C D E F DDRAM LINE 1 (00H~0FH) DDRAM LINE 2 (10H~1FH) DDRAM LINE 3 (20H~2FH) DDRAM LINE 4 (30H~3FH) CGRAM (pattern 0) CGRAM (pattern 2) CGRAM (pattern 4) CGRAM (pattern 6) CGRAM (pattern1) CGRAM (pattern 3) CGRAM (pattern5) CGRAM (pattern 7)
Read Data from CGRAM/DDRAM or ICONRAM
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
1
1
D7 D6 D5 D4 D3 D2 D1 D0
Before RAM data read, address set of either CGRAM/DDRAM or ICONRAM should be performed. The first read is a dummy read. The data is invalid. The correct data is obtain from the second read. After read data the address counter will increase by 1 automatically. If multiple read in succession only the first read data is dummy.
Ver 2.1
22/43
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ST7093
Line shift mode
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
0
0
0
0
0
1
1
0 LS2 LS1
Set Line Shift mode LS2 Low Low High High LS1 Low High Low High Action DDRAM Line1 shows at the first line of LCD (default) DDRAM Line2 shows at the first line of LCD DDRAM Line3 shows at the first line of LCD DDRAM Line4 shows at the first line of LCD
Reset Function
Initializing by Internal Reset Circuit External reset can be achieved by pulling low RESETB pin. 1. Function set: S = 0; COM left shift CG = 0; CGRAM disable 2. Display on/off control: D = 0; Display off C = 0; Cursor off B = 0; Blinking off 3. Power control & bias BS = 0 ; 1/5 bias OS = 0 ; oscillator off PS = 0 ; power save off VC = 0; voltage booster off VR = 0; voltage regulator off VF = 0; voltage follower off 4. Line shift mode (LS2,LS1) = (0,0) ; DDRAM line 1 shown at the first line of LCD display 5. Electronic contrast control register (E4,E3,E2,E1,E0) = (0,0,0,0,0) RESETB pulse width RESET start time Trw Tres 10us 50ns
Ver 2.1
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ST7093
VDD Tres RESETB
Trw
Ver 2.1
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ST7093
Interfacing to the MPU
The ST7093 can send data in either two 4-bit operations or one 8-bit operation, or 4 pin clock synchronous serial interface is used. For 4-bit interface data, only four bus lines (DB4 to DB7) are used for transfer. Bus lines DB0 to DB3 are disabled. The data transfer between the ST7093 and the MPU is completed after the 4-bit data has been transferred twice. As for the order of data transfer, the four high order bits (for 8-bit operation, DB4 to DB7) are transferred before the four low order bits (for 8-bit operation, DB0 to DB3). For 8-bit interface data, all eight bus lines (DB0 to DB7) are used. For serial interface, by setting PS = "Low" DB7 become SI (serial in data), DB6 become SCL (serial clock). Each bit of data transfer is at the rising edge of SCL. At the rising edge of 8th SCL the data is converted into 8 bit parallel data and RS bit is read in to select whether write data or write instruction. Read operation is not supported. CSB SI SCL RS
100us
D7 D6 ...........D0
100us D7 D6 ....... D0
Timing Diagram of Serial Mode Data Transfer (serial Mode) Supply Voltage for LCD Drive
There are different voltages that supply to ST7093's pin (V0 - V4) to obtain LCD drive waveform. The relations of the bias, duty factor and supply voltages are shown as below: Duty Factor 1/17 Bias Supply Voltage V0 V1 V2 V3 V4 1/4 VLCD 3/4 VLCD 1/2VLCD 1/2VLCD 1/4 VLCD 1/5 VLCD 4/5 VLCD 3/5 VLCD 2/5 VLCD 1/5 VLCD
Ver 2.1
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2003/09/23
ST7093
Initialization sequence
Power On RESETB = 0
Wait 10us RESETB = 1 Wait 10us Power save(PS, OS) Function set (S,CG) Power control(VC,VR,VF) Electronic contrast set
Wait time > 20ms
Clear DDRAM Clear CGRAM Clear ICONRAM
Display on
Initialization End
Ver 2.1
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ST7093
Sleep mode set
End of initialization
Normal operation (PS=0 , OS=1)
Display off (D=0) Power save (PS=1 , OS=0) Power control off (VC=0, VR=0, VF=0)
Enter sleep mode
Sleep mode release
Sleep mode
Power save (ps=0, os=1) Power control on (VC=1,VR=1,VF=1)
Wait more than 20ms
Display on (D=1) Resume normal operation
Ver 2.1
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ST7093
Power off sequence
Normal operation
Display off (D=0) Power save (PS=1, OS=0) Power control off (VC=0,VR=0,VF=0)
Wait more than 10ms
Power off
Ver 2.1
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2003/09/23
ST7093
Voltage booster
The voltage booster use internal generates reference voltage 1.8V to boost 4 times to produce Vout as 7.2V.
vout +
1.8V X 4 =7.2V
Vdd
+ -
Cap1+
Cap1-
1.8v vss Voltage regulator
+ -
Cap2+
Cap2Vout
The voltage regulator circuit is used to obtain an appropriate LCD panel driving voltage. This voltage is obtained By adjusting resistors Ra and Rb as shown in equation (1) or (2) ,and by setting Electronic Contrast Control data Bits, see this equation (3) or (4). The potential of V0 Pin can be adjusted within Vout - Vref, Vref is the internal constant voltage source of the Chip and this value is 2.0V in the condition vdd 2.4V The REF selects which voltage is used for voltage regulator between the ecternal VEXT and internal Vref. Voltage regulation by adjusting resistors Ra, Rb
Rb Vout VR VEXT + + Vo
When REF is "Low" V0 = ( 1 + Rb / Ra ) x Vref........(1) When REF is "High" V0 = ( 1 + Rb / Ra ) x VEXT .....(2) Reference set value Ra = 1M Rb = 1.5M
Ra
REF Vref Vss Inside Chip
GND
Ver 2.1 29/43
Voltage regulator circuit
2003/09/23
ST7093
Electronic contrast control (32 steps)
Electronic contrast control data bits is 10H = (C4, C3, C2, C1, C0 ), Voltage regulation is adjusted as 32-contrast step According to the value of Electronic contrast control data bits. LCD drive voltage V0 has one of 32 voltage values if 5-bit data is set to the electronic contrast control register (ICONRAM address 10H). When using the electronic contrast control function, you need to turn the voltage regulators on using power control instruction.
When REF is "Low" V0 = ( 1 + Rb / Ra ) x Ven ..... (3) Ven = Vref - n ( n = 0, 1, 2, ..... 30, 31 ) = Vref / 150 When REF is "High" V0 = ( 1 + Rb / Ra ) x Ven ..... (4) Ven = Vext - n ( n = 0, 1, 2, ..... 30, 31 ) = Vext / 150
Rb Vout VR VEXT + Vss GND
Electronic contrast control circuit
+ + Ven - Inside Chip
Vo
REF
Ra
Vref
No. 1 2 3 4 . . . 31 32
C7 C6 C5 C4 -0 -0 -0 -0
-
-
-
n V0 Contrast 0 (default) Maximum High 1 . . 2 . . 3 . . . . . . . . . . . 11110 30 . . 11111 31 Minimum Low Electronic contrast control register ("-" don't care)
C3 C2 C1 C0 0000 0001 0010 0011
Ver 2.1
30/43
2003/09/23
ST7093
Voltage generator circuit
VDD
+
C1 C1
Vdd Cap1+ Cap1Cap2+ Cap2Vout VR
Ra GND
Rb
-+
C2 C2 C2 C2 C2
V0 V1 V2 V3 V4 Vss
C1: 0.1 .. 4.7Uf C2: 0.1uF Ra: 1M Rb:1.5M
GND
When built-in power supply is used (VC,VR,VF = 1,1,1)
VDD Vdd Cap1+ Cap1Cap2+ Cap2Vout VR Rb GND -+ V0 V1 V2 V3 V4 Vss -+
C2 C2 C2 C2 C2 External Power supply
VDD Vdd Cap1+ Cap1Cap2+ Cap2Vout VR
VDD Vdd Cap1+ Cap1Cap2+ Cap2Vout VR
External l
GND Ra GND
C2 C2 C2 C2 C2
V0 V1 V2 V3 V4 Vss
External Power supply
V0 V1 V2 V3 V4 Vss
GND
GND
GND
(VC,VR,VF= 0,1,1)
(VC,VR,VF= 0,0,1)
(VC,VR,VF= 0,0,0) (C2:01 to 4.7uF)
When external power supply is used
Ver 2.1 31/43
2003/09/23
ST7093
MPU Interface
VCC A0 A1-A7 IORQ /RD /WR D0~D7 /RES RESETB RS Decoder CSB E_RD RW_WR DB[0~7] RESETB
VDD PS MI
8080 series MPU
ST7093
IF VSS
GND
Parallel interfacing with 8080-series microprocessors.
VCC A0 A1-A7 /VMA R/W E DB[0~7] /RES RESETB RS Decoder CSB RW_WR E_RD DB[0~7] RESETB
VDD PS MI
6800 series MPU
ST7093
IF VSS
GND
Parallel interfacing with 6800-series microprocessors.
Ver 2.1
32/43
2003/09/23
ST7093
Fixed to high
VCC PORT4 RS
VDD IF MI
ST7093 MPU
PORT3 PORT1 PORT2 /RES GND RESETB CSB
RW_WR SCL(DB6) E_RD SI(DB7) DB0~DB5 RESETB PS VSS
Clock synchronized serial interfacing with any microprocessors.
Ver 2.1
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2003/09/23
ST7093
Absolute Maximum Ratings
Characteristics Power Supply Voltage LCD Driver Voltage Input Voltage Operating Temperature Storage Temperature Symbol VDD VLCD VIN TA TSTO Value -0.3V to +7.0V -0.3V to +10.0V -0.3V to VDD+0.3V -40oC to + 85oC -55oC to + 125oC
DC CHARACTERISTICS ( TA = 25oC , VDD =2.4V - 3.6V )
Symbol VDD VLCD IDD Characteristics Operating Voltage LCD Voltage Power Supply Current VIH1 VIL1 VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 RCOM RSEG ILEAK Input High Voltage (Except OSC1) Input Low Voltage (Except OSC1) Input High Voltage (OSC1) Input Low Voltage (OSC1) Output High Voltage (DB0 - DB7) Output Low Voltage (DB0 - DB7) Output High Voltage (Except DB0 - DB7) Output Low Voltage (Except DB0 - DB7) Common Resistance Segment Resistance Input Leakage Current VLCD = 4V, Id = 0.05mA VLCD = 4V, Id = 0.05mA VIN = 0V to VDD -1 2 2 20 30 1 K K A IOL = 0.04mA 0.2 VDD V IOH = -0.04mA 0.8VDD VDD V IOL = 0.1mA 0.4 V IOH = -0.1mA 0.8VDD VDD V 1.0 V VDD - 1 VDD V - 0.3 0.6 V Condition V0- VSS fOSC = 160KHz, VDD =3.0V checker pattern no CPU access 0.7VDD VDD V Min. 2.4 3.0 Typ. 90 Max. 3.6 7.0 115 Unit V V uA
Ver 2.1
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2003/09/23
ST7093
AC CHARACTERISTICS (TA = 25oC, VDD = 2.7 V - 3.6 V)
Symbol Characteristics Test Condition Internal Clock Operation fOSC fEX TR,TF OSC Frequency External Clock Operation External Frequency Duty Cycle Rise/Fall Time 112 45 160 50 208 55 0.2 KHz % s 112 160 208 KHz Min. Typ. Max. Unit
Ver 2.1
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ST7093
TIMING CHARACTERISTICS
Writing data from MPU TO ST7093 by 68 mode parallel interface
RS,CSB
VIH1 VIL1 TAS TAH
RW_WR
TPW TAH
E_RD
TR TDSW Valid data TC TH
DB0-DB7
Reading data from ST7093 TO MCU by 68 mode parallel interface
RS,CSB RW_WR
TR
VIH1 VIL1 TAS TAH
TPW
TAH
E_RD
TDDR TH Valid data TC
DB0-DB7
Ver 2.1
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ST7093
68 INTERFACE READ/WRITE TIMING(TA = 25oC, VDD =3.6V)
Symbol TC WRITE MODE TPW TR,TF TAS TAH TDSW TH TC TPW READ MODE TR,TF TAS TAH TDDR TH Characteristics Test Condition Min. 100 300 100 20 150 20 100 300 360 20 50 Typ. Max. 25 25 300 Unit us ns ns ns ns ns ns us ns ns ns ns ns ns Enable Cycle Time Pin E Enable Pulse Width Pin E Enable Rise/Fall Time Pin E
Address Setup Time Pins: RS,RW,CSB Address Hold Time Pins: RS,RW,CSB Data Setup Time Data Hold Time Pins: DB0 - DB7 Pins: DB0 - DB7
Enable Cycle Time Pin E Enable Pulse Width Pin E Enable Rise/Fall Time Pin E
Address Setup Time Pins: RS,RW,CSB Address Hold Time Pins: RS,RW,CSB DB output ready Time Pins: DB0 - DB7 DB output Hold Time Pins: DB0 - DB7
68 INTERFACE READ/WRITE TIMING (TA = 25oC, VDD = 2.7V)
Symbol TC TPW TR,TF TAS TAH TDSW TH TC TPW TR,TF TAS TAH TDDR TH Characteristics Enable Cycle Time Enable Pulse Width Enable Rise/Fall Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Test Condition Pin E Pin E Pin E Pins: RS,RW,CSB Pins: RS,RW,CSB Pins: DB0 - DB7 Pins: DB0 - DB7 Min. 100 300 500 20 300 20 100 300 580 20 50 Typ. Max. 25 25 340 Unit us ns ns ns ns ns ns us ns ns ns ns ns ns
WRITE MODE
Enable Cycle Time Pin E Enable Pulse Width Pin E Enable Rise/Fall Pin E Time Address Setup Time Pins: RS,RW,CSB Address Hold Time Pins: RS,RW,CSB DB output ready Time Pins: DB0 - DB7 DB output Hold Time Pins: DB0 - DB7
Ver 2.1
READ MODE
37/43
2003/09/23
ST7093
Writing data from MPU to ST7093 by 80 mode parallel interface
RS,CSB
VIH1 VIL1 TAS TAH
E_RD
TPW
RW_WR
TF TDSW Valid data TC TH
DB0-DB7
Reading data from ST7093 to MPU by 80 mode parallel interface
RS,CSB
VIH1 VIL1 TAS TAH
RW_WR
TPW
E_RD
TDDR TH Valid data TC
DB0-DB7
Ver 2.1
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ST7093
80 INTERFACE READ/WRITE TIMING (TA = 25oC, VDD = 3.6V)
Symbol TC TPW TR,TF TAS TAH TDSW TH TC TPW TR,TF TAS TAH TDDR TH Characteristics Test Condition Enable Cycle Time Pin E Enable Pulse Width Pin E Enable Rise/Fall Pin E Time Address Setup Time Pins: RS,RW,CSB Address Hold Time Pins: RS,RW,CSB Data Setup Time Pins: DB0 - DB7 Data Hold Time Pins: DB0 - DB7 Enable Cycle Time Pin E Enable Pulse Width Pin E Enable Rise/Fall Pin E Time Address Setup Time Pins: RS,RW,CSB Address Hold Time Pins: RS,RW,CSB DB output ready Time Pins: DB0 - DB7 DB output Hold Time Pins: DB0 - DB7 Min. 100 300 40 200 180 40 100 300 360 20 50 Typ. Max. 25 25 300 Unit us ns ns ns ns ns ns us ns ns ns ns ns ns
80 INTERFACE READ/WRITE TIMING (TA = 25oC, VDD = 2.7V)
Symbol TC TPW TR,TF TAS TAH TDSW TH TC TPW TR,TF TAS TAH TDDR TH Characteristics Test Condition Enable Cycle Time Pin E Enable Pulse Width Pin E Enable Rise/Fall Pin E Time Address Setup Time Pins: RS,RW,CSB Address Hold Time Pins: RS,RW,CSB Data Setup Time Pins: DB0 - DB7 Data Hold Time Pins: DB0 - DB7 Enable Cycle Time Pin E Enable Pulse Width Pin E Enable Rise/Fall Pin E Time Address Setup Time Pins: RS,RW,CSB Address Hold Time Pins: RS,RW,CSB DB output ready Time Pins: DB0 - DB7 DB output Hold Time Pins: DB0 - DB7 Min. 100 300 40 380 280 40 100 300 440 40 50 Typ. Max. 25 25 340 Unit us ns ns ns ns ns ns us ns ns ns ns ns ns
Ver 2.1
READ MODE
WRITE MODE
READ MODE
WRITE MODE
39/43
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ST7093
Writing data from MPU TO ST7093 by Serial mode interface
tSU1 tC tH1
CSB
tR tW
tW tF
SCL
tSU2
tH2
RS
tSU3 tH3
SI
SERIAL INTERFACE WRITE TIMING
Symbol TC TW TR,TF TSU1 TH1 TSU2 TH2 TSU3 TH3 Characteristics Enable Cycle Time Enable Pulse Width Enable Rise/Fall Time CSB Setup Time CSB Hold Time Rs Data Setup Time Rs Data Hold Time SI Data Setup Time SI Data Hold Time
(TA = 25oC, VDD = 3.6V)
Min. 3.0 1.5 20 100 40 40 40 40 Typ. Max. Unit us us ns ns us ns ns ns ns
WRITE MODE
Test Condition Pin SCL Pin SCL Pin SCL Pin CSB Pin CSB Pin RS Pin RS Pin SI Pin SI
25
SERIAL INTERFACE WRITE TIMING
Symbol TC TW TR,TF TSU1 TH1 TSU2 TH2 TSU3 TH3 Characteristics Enable Cycle Time Enable Pulse Width Enable Rise/Fall Time CSB Setup Time CSB Hold Time Rs Data Setup Time Rs Data Hold Time SI Data Setup Time SI Data Hold Time
(TA = 25oC, VDD = 2.7V)
Min. 5.0 2.5 20 100 40 40 40 40 Typ. Max. Unit us us ns ns us ns ns ns ns
WRITE MODE
Test Condition Pin SCL Pin SCL Pin SCL Pin CSB Pin CSB Pin RS Pin RS Pin SI Pin SI
25
Ver 2.1
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2003/09/23
ST7093
I/O PAD Configuration
Control Data Data
Input PADs without pull up PMOS
Input PADs with pull up PMOS
Enable
Cont Data
DATA
I/O PADs with pull up PMOS
When PS=1 all inputs and I/O pins are without PMOS pull up.
When PS=0 since only CSB, RS and DB6, DB7 is used for data transmission therefore RW_WR, E_RD and DB0~DB5 has internal pull up PMOS. All system configuration pins such as CK,MI,PS,IF and DIRS are without pull up.
Ver 2.1
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2003/09/23
ST7093
Typical application
5x8 dots, 16 characters x 2 line (1/5 bias, 1/17 duty)
COM1 . . . . . COM8
ST7093A
COM9 . . . . . . COM16 COMI1 SEG1 . . . . . . . SEG80 LCD Panel: 16 Characters x 2 line
Ver 2.1
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2003/09/23
ST7093
ST7093 Specification Revision History Version 0.1A 0.2A Date 2000/06/12 2000/10/01 Description 1. 17com*60segment (Original) 1. 26com*80segment 1. Changed DC characteristics VLCD=V0-VSS 0.3 2001/01/08 2. CGROM standard font 0B&C0A 3. Modify 3-Line mode double height instruction 4. Modify AC characteristics 1. Modify Booster 2.4Vx4 1.8Vx4 (page 27) 2. 2line17duty,3line25duty (Page 10) 0.3B 2001/03/12 3. COG Align Key Coordinate (page 4) 4.Reference Ra,Rb value (page 27,29) 5. Modify pin description CK , D0..D3 , TEST pin 0.4 2001/04/17 1. Modify AC characteristics
0.4b
2002/02/07
1. Add COB Pad Dimensions 1. Modify double height mode instruction ( P16 & P18 ) 2. Add illustration of electronic contrast control circuit ( P30 )
1.0
2002/05/23
3. Add illustration of voltage regulator circuit ( P29 ) 4. Add illustration of MPU interface ( P32 & P33 )
2.0
2002/08/29
1. Modify Operating Voltage 2.4V .. 3.6V 1. Modify CK pin must fixed "Vss" 2. CGROM standard font 0C 1. Modify product number to ST7093
2.0b
2002/09/05
2.1
2003/09/23
Ver 2.1
43/43
2003/09/23

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